The present invention relates generally to a method of encapsulating a semiconductor package assembly or an array of such semiconductor package assemblies typically arranged on a supporting panel, while protecting the package""s exposed terminals.
In the construction of semiconductor chip package assemblies, it has been found desirable to interpose encapsulating material between and/or around elements of the semiconductor packages in an effort to reduce and/or redistribute the strain and stress on the connectors between the semiconductor chip and a supporting circuitized substrate during operation of the chip, and to seal the elements against corrosion, as well as to insure intimate contact between the encapsulant, the semiconductor die and the other elements of the chip package.
It is often desirable to package a semiconductor chip assembly such that it can be handled with less fear of damage to the assembly so that a heat sink can be married with the semiconductor chip. However, if a semiconductor chip assembly is to be so packaged, the utmost care must be taken during the packaging process to avoid affecting the integrity of the terminals on the chip carrier. In particular, it is important to avoid contaminating the terminals on the chip carrier with the encapsulant.
Certain designs have reduced solder connection fatigue by redistributing the thermal cycling stress into a portion of the chip package itself. An example of such a design is shown in U.S. Pat. Nos. 5,148,265 and 5,148,266, the both disclosures of which are incorporated herein by reference. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a compliant layer to reduce the coefficient of thermal expansion (xe2x80x9cCTExe2x80x9d) mismatch problems. Typically, the compliant layer includes an elastomeric layer which, in the finished package, it disposed between the chip carrier and the face surface of the chip. The compliant layer provides resiliency to the individual terminals, allowing each terminal to move in relation to its electrically connected chip contact to accommodate CTE mismatch as necessary during testing, final assembly and thermal cycling of the device.
In some arrangements used heretofore, the compliant layer is formed by stenciling a thermoset resin onto the chip carrier and then curing the resin. Next, additional resin is applied to the exposed surface of the cured layer, this additional resin is partially cured, and the resulting tacky adhesive surface was used to bond the elastomeric layer to the chip and the chip carrier. Once attached, the entire structure is heated and fully cured. The leads are then bonded to respective chip contacts. An encapsulant material is then disposed under and around the leads from the terminal side of the assembly. This process amounts to very carefully depositing a controlled amount of encapsulant on the periphery of the contact surface of the chip from the terminal side of the assembly, building layer upon layer of encapsulant until the leads are fully encapsulated. In such a process, the encapsulant is held in place by the surface tension of the encapsulant material between the dielectric layer and the contact bearing surface of the chip. Using such a method, the encapsulant material may creep on to the exposed surface of the dielectric layer potentially contaminating the terminals and also overcoming the surface tension of the encapsulant further causing the encapsulant to get onto other surfaces of the assembly or onto adjacent chip assemblies.
Accordingly, a method of controlling the encapsulation of a semiconductor chip package assembly such that the integrity of the terminals and leads are not affected is desirable.
The present invention provides a method of encapsulating a semiconductor device and associated package structures.
The method according to the present invention includes a method of packaging a plurality of semiconductor chips in which a compliant spacer layer is disposed between a top surface of a sheet-like substrate and surface of each semiconductor chip, wherein the semiconductor chip has contacts a surface thereof and wherein the substrate has terminals at least some of which lie outside the periphery of the chip. The substrate terminals and the chip contacts are then electrically connected to one another by flexible, electrically conductive lead. A unitary support structure is then aligned with the chips and attached to or abutted against the compliant layer around the periphery of the chips. A curable liquid encapsulant is then deposited around at least a portion of the periphery of each chip on top the unitary support structure so as to encapsulate the leads and at least one surface of the chip. Alternately, the curable liquid encapsulant may deposited around at least a portion of the periphery of each chip so as to encapsulate the leads and at least one surface of the chip and the unitary support structure may then aligned with the chips and attached to (and/or embedded in) the encapsulant around the periphery of the chips. The unitary support structure may be conductive (electrically or thermally) or insulative and further may have apertures or slots therein for reducing voids or bubbles between the unitary support structure and the encapsulant during the attached step. Optionally, a additional step of applying uniform pressure to the chip assemblies prior to the curing step may be employed such that such pressure reduces voids or bubbles between the unitary support structure and the encapsulant. The encapsulant is then cured to define an integrated composite of chip packages which may be singulated into individual chip packages or into multi-chip modules. Typically, the substrate is held taut of a frame during the packaging process.
The structures according to the present invention include a multi-chip frame assembly comprising a frame having a central aperture and a flexible substrate having electrical leads and terminals, said substrate being attached to the frame across the aperture. A plurality of chips, each having a plurality of chip contacts, are attached to the substrate such that at least some of the substrate terminals are lying outside the periphery of the chips. The chip contacts are electrically connected to respective substrate terminals. A unitary support structure having a plurality of apertures therethrough is attached to the substrate within the central aperture of the frame such that at least some of the substrate terminals underlying the unitary support structure. A compliant layer is disposed between the chip and the substrate and the unitary support structure and the substrate. The assembly of parts thereby defining an integrated composite of chip packages.
In one preferred embodiment of the present invention, the compliant spacer layer is comprised of a plurality of compliant pads which are disposed between the substrate and the chips. Such compliant pads may also be disposed around the periphery of the chips for engagement with the unitary support structure so as to facilitate planarizing the unitary support structure along the length and width of the assembly.
The unitary support structure may be a sheet-like ring element having a plurality of apertures therethrough such that the aligning step registers each aperture with a respective chip such that each chip is at least partially received within a respect aperture. In one embodiment, a sheet like thermal spreader may be attached to the exposed major surface of such a ring element type unitary support structure to create a fully enclosed unit around each chip. In another embodiment, such a ring element type unitary support structure and the frame may be integral with one another such that they can be manufactured in a single process, such as etching or stamping. In still a further embodiment, the unitary support structure may be comprised of a plurality of substantially, integral continuous cap structures having a plurality of cavities, such that the cap structures are aligned with the chips so that each of the cavities at least partially receives a respective chip therein. Such a cap type unitary support structure would preferably be thermally conductive. Also, such a cap type unitary support structure preferably has grooves in a exposed surface to facilitate the singulation of the chip packages from one another. Also, there may be more than one unitary support structure which are aligned with the chips and attached to the encapsulant.
In a further variant of the present invention, the chips may be oriented such that the chip contacts face away from the substrate. In such an embodiment, if a cap type unitary support structure is employed, it may have a similar coefficient of thermal expansion to that of semiconductor chips so as to constrain the leads and encapsulant between the unitary support structure and each of the chips.
The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of a Preferred Embodiment, taken together with the attached Figures.
FIG. 1 is a side cross-sectional view, illustrating a semiconductor chip package assembly being encapsulated in an inverted position within a frame, according to the present invention.
FIG. 2 is a side cross-sectional view of a singulated device having bumpers around the periphery of the chip package assembly, according to the present invention.
FIGS. 3A and 3B show various views of the encapsulation technique shown in FIG. 1 used with a plurality of devices on a common frame, according to the present invention.
FIG. 4A is a side cross-sectional view of a singulated chip package assembly, according to the present invention.
FIG. 4B is a face view of the chip package assembly shown in FIG. 4A, according to the present invention.
FIG. 5 is a side cross-sectional view of a singulated device having bumpers around the periphery of the chip package assembly and further having terminals beyond the periphery of the periphery of the chip, according to the present invention.
FIGS. 6A-6G show the process steps for encapsulating a center bonded semiconductor chip package assembly, according to the present invention.
FIGS. 7A-7G show the process steps for encapsulating a center bonded semiconductor chip package assembly as shown in FIGS. 6A-6G with a flexible membrane attached thereto, according to the present invention.
FIG. 8 is a side cross-sectional view of a singulated device having bumpers around the periphery of the chip package assembly and further having a protective membrane attached to the exposed surfaces of the chip and bumpers, according to the present invention.
FIGS. 9A-9D show the process steps for encapsulating a semiconductor chip package assembly in which the chip carrier is encapsulated leaving only the raised terminals to protrude from the face surface of the chip package, according to the present invention.
FIGS. 10A-10D show a process similar to that shown in FIGS. 9A-9D except that the raised terminals are removed after the encapsulation/cure steps, according to the present invention.
FIG. 11 shows a cross-sectional side view of a so called fan-in/fan-out embodiment of the present invention.
FIGS. 12A-12G show the process steps for manufacturing a center bonded semiconductor chip package assembly and the resulting package structure, according to the present invention.
FIG. 13A shows a top plan view of a semiconductor chip assembly having a unitary support structure, according to the present invention.
FIG. 13B is a cross-sectional side view of the semiconductor chip assembly in FIG. 13A.
FIG. 13C is a cross-sectional side view of the resulting chip package assembly in FIG. 13A after singulation.
FIGS. 14A-14D is a fragmentary top plan view showing various unitary support structures, according to the present invention.
FIG. 15A shows a cross-sectional side view of another semiconductor chip assembly, according to the present invention.
FIG. 15B shows a cross-sectional side view of another semiconductor chip assembly, according to the present invention.
FIG. 16 shows a cross-sectional side view of another semiconductor chip assembly, according to the present invention.